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features ? dc to dc converter 1.9v / 2.5v (dcdc1) ldo regulator 2.7v / 2.8v (ldo1) ldo regulator 2.8v (ldo2) ldo regulator 2.8v (ldo3) ldo regulator 2.47v / 2.66 (ldo 4) - backup battery supply ldo regulator 1.72v / 2. 66 (ldo5) - rtc supply reset generator 1. description the at73c211 is a power management device for digital, analog, interface, and, in some cases, rf and backup sections of add-on modules used as accessories in pop- ular handheld devices like mobile phones, digital still cameras, pdas and a wide range of multimedia devices. the at73c211 can also be used to supply the cpu with a high-efficiency dc-dc converter, a r adio frequency transceiver with high power supply rejection ratio (psrr) and noise performance low-dropout (ldo) regulators, or memories and analog sections with independent ldo channels. in addition, the at73c211 integrates ldo r egulators to recharge backup elements and convert its voltage to microcontroller rtc supply. ldo regulators and dc-dc converters output voltage can be programmed by a mask change. power management at73c211 6199a?pmgmt?20-sep-05
2 6199a?pmgmt?20-sep-05 at73c211 2. functional block diagram figure 2-1. at73c211 block diagram reset generator 35ms vpad reset-b dgnd vin en fb gnd core dc/ dc gnd vcore 1.9/2.5v / 300 ma vcore gnd1 vin en vout gnd vin en vout gnd analog ldo avcc agnd vin en gnd pad ldo vback vbatt on/off up-on/off vin-reg1 vin-reg2 agnd rtc supply block vpad gnd vbatt 2.8v / 80 ma en-analog-b deep discharged 2.6v vin en vout gnd vib -out vvib en-vib gnd gnd lx v-vib 2.8v /130 ma eco-mode lx avcc 2.7/ 2.8v / 130 m a bb1 2.8v lp dcdc gnd lp vibrator ldo dgnd bb1 agnd1 gnd gnd en-analog-b vbatt pmc state machine ls spi por 10khz osc over-temp en up-on/off on/off eco-mode gnd en state machine reset reset bat-rtc 2.47 /2.66v 5 ma vcc-rtc 1.72 /2.66v 0.5ma vcc-rtc bat-rtc gnd gnd 2.7v bb1 gnd vref cref agnd v-pad vbatt cref reset-b en en_vcore en_vcore bb1 gnd test en_vpad vbatt>3.2v en gnd en_vcore ldo1 ldo2 ldo3 ldo4 ldo5 vbatt vbatt v-pad
3 6199a?pmgmt?20-sep-05 at73c211 3. pin description table 3-1. pin description signal pin type a/d description vbatt e1 vbatt1 input supply on/off d5 ipd d key on/off input, 1.5m ohm pull-down up-on/off c6 i d hold the power on from mcu reset-b f6 od d reset open collector outp ut. need external pull-up to vbatt vin-reg1 g6 vbatt2 input supply for dc/dc converter lx f7 o a dc/dc converter output inductor eco-mode g5 ipd d eco mode, from mcu - sets vcore, v-pad in low power mode, 1.5m ohm pull-down vcore g4 o a dc/dc converter output (mcu core supply) gnd1 g7 ground ground of dc/dc converter vin-reg2 a5 vbatt3 input supply en-analog-b b5 ipd d enable the analog ldo, active at logic 0, 1.5m ohm pull-down avcc b4 o a analog ldo output (mcu chip analog supply) agnd a7 ground ground of avcc, v-pad and rtc ldo v-pad b6 o a digital ldo output (mcu chip digital pad supply) vcc-rtc b7 o a mcu rtc supply output bat-rtc a6 i/o a rtc backup battery charger - must be connected through a 2.2k ohm resistor to the backup battery vin-rf a3 vbatt4 input supply agnd2 a2 ground ground vin-vib d7 vbatt5 input supply for vibrator ldo en-vib e6 ipd d vibrator driver input (from baseband chip), 1.5m ohm pull-down vvib e7 o a vibrator ldo output (voltage regulator) gnd d1 ground ground cref c7 o a bandgap decoupling - 100 nf capacitor must be connected from this pin to ground bb1 d4 i d bb1 = 1 => vcore = 2.5v, bb1= 0 => vcore = 1.9v test e5 ipd a connect to agnd
4 6199a?pmgmt?20-sep-05 at73c211 4. functional description 4.1 dc to dc converter 1.9v/2 .5v - 300 ma for coprocessor core the dc-to-dc converter is a synchronous mo de dc-to-dc ?buck?-switch ed regulator using fixed-frequency architecture (pwm) and capable of providing 300 ma of continuous current. it has two levels of voltage programming for the co-processor core (1.9v or 2.5v). the operating supply range is from 3.1v to 5.5v, making it suitable for li-ion, li-polymer or ni-mh battery applications. the dc-to-dc converter is based on pulse width modulation architecture to con- trol the noise perturbation for switching noise sensitive applications (w ireless). the operating frequency is set to 900 khz using an internal clock, allowing the use of a small surface induc- tor and moderate output voltage ripple. the controller consists of a reference ramp generator, a feedback comparator, the logic driver used to drive the internal switches, the feedback cir- cuits used to manage the different modes of oper ation and the over-current protection circuits. an economic mode has been defined to reduce quiescent current. a low-dropout voltage reg- ulator in parallel to the dc-to-dc converter minimizes standby current consumption during standby mode. figure 4-1. dual-power dc-to-dc converter low undershoot voltage is expected when going from pwm to ldo mode and vice-versa. the circuit is designed in order to avoid any spikes when transition between two modes is enabled. figure 4-2. low-power/full-powe r dc-to-dc converter transition v batt eco-mode dc-to-dc buck 1.9v or 2.5v 300 ma internal fet ldo 1.9v or 2.5v 10 ma low power v core l c low power high power v core eco-mode high power low power v core eco-mode
5 6199a?pmgmt?20-sep-05 at73c211 figure 4-3 shows typical efficiency levels of the dc-to-dc converter for several input voltages. figure 4-3. dc-to-dc converter with 1.9v target typical case (1) note: 1. l = 10 h, esr = 0.2 ohm, c = 22 f, @esr = 0.1 ohm 4.2 ldo1, ldo3 regulators the psrr measures the degree of immunity agai nst voltage fluctuations achieved by a regu- lator. an example of its importance is in the case of a gsm phone when the antenna switch activates the rf power amplifier (pa). this causes a current peak of up to 2a on the battery, with an important spike on the battery voltage. the voltage regulator must filter or attenuate this spike. 70 75 80 85 90 95 100 0 50 100 150 200 250 300 350 400 load current (ma) efficiency (%) vin=3.1v vin=3.6v vin=4.2v
6 6199a?pmgmt?20-sep-05 at73c211 figure 4-4. functional diagram of ldo single mode figure 4-5 shows the power supply rejection ratio as functions of frequency and battery volt- age. if a noise signal occurs at 1 khz when the battery voltage is at 3v, the noise will be attenuated by 70 db (divided by more than 3000) at the output of the regulator. consequently, a 2v spike on the battery is attenuated to le ss than 1 mv, which is low enough to avoid any risk of malfunction by a device supplied by the regulator. figure 4-5. power supply rejection ratio in function of frequency and battery voltage ibias v int v bg on on v batt pass device on current sensing and limiter r1 r2 on on v outs v out gnd gnd gnd gnd v out1 v out2 pow er supply rejection ratio at full load -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 10 100 1000 10000 100000 fr e q [hz ] psrr [d b] v bat = 3v v bat = 4.25v v bat = 5.5v pow er supply rejection ratio at full load ve rsus ba tte ry volta ge -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 3.0 3.5 4.0 4.5 5.0 5.5 ba tte ry v olta ge [v ] psrr [db] freq = 100 hz freq = 1 khz freq = 20 khz freq = 100 khz
7 6199a?pmgmt?20-sep-05 at73c211 4.3 ldo2 regulator the first approach to reducing standby current is to decrease the standby current inside the regulators themselves. atmel achieves this by implementing a dual mode architecture where two output transistors are used in parallel as switches in the regulation loop. figure 4-6 illus- trates this architecture. figure 4-6. functional diagram of ldo dual mode in figure 4-6 , the left-hand output transistor is sized large enough for the required output cur- rent under full load, for example, 100 ma. in order to achieve a sufficient margin of stability, the current sensing block uses a bias cell where the current consumption is linked to the required output current. the higher the output current, the higher the bias current needed to stabilize the loop. the right-hand output transistor delivers a very small output current, typically less than 1 ma, sufficient only to maintain the output voltage with enough current to cover the leakage current of the supplied device. this requires a much sm aller bias current and, consequently, a smaller standby current inside the regulator. v out v out v bg v bg on on on lp on lp gnd gnd gnd on lp r1 r2 bias on current sensing and limiting gnd gnd on, lp v batt v core v vout1 v vout2
8 6199a?pmgmt?20-sep-05 at73c211 5. electrical characteristics 5.1 absolute maximum ratings 5.2 dc to dc converter operating temperature (industrial).............. -40 c to +85 c *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the opera- tional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. storage temperature .................................. -55c to +150c power supply input pads............ ................... -0.3v to +5.5v i/o input (all except to power supply) ........... -0.3v to +3.3v table 5-1. dc to dc converter electrical characteristics (t amb = -20 c to 85 c, vin = 3.2v to 4.2v unless otherwise specified) symbol parameter conditions min typ max unit v out output voltage bb1 = 0 1.9 v bb1 = 1 2.5 v i out output current pwm mode (eco-mode = 0) 150 300 ma ldo mode (eco-mode = 1) 5 ma i off standby current 0.1 1 a e ff efficiency i out = 10 ma to 200 ma @1.9v 90 % ? v dcld static load regulation 10% to 90% of i out(max) 7mv ? v trld transient load regulation 10% to 90% of i out(max) , t r = t f = 5s 30 mv ? v dcle static line regulation 10% to 90% of i out(max) , vin = 3.2v to 4.2v 20 mv ? v trle transient line regulation 10% to 90% of i out(max) , vin = 3.2v to 4.2v 35 mv psrr ripple rejection ldo mode up to 1 khz 40 45 db ? v lpfp overshoot voltage voltage drop from ldo (eco- mode = 1) to pwm (eco- mode = 0) 010mv ? v fplp undershoot voltage voltage drop from pwm (eco- mode = 0) to ldo (eco-mode = 1) -15 0 mv table 5-2. dc to dc converter external components symbol parameter conditions min typ max unit c out output capacitor value 17 22 26 f c esr output capacitor esr 100 mohm l out output inductor value 8 10 12 h l esr output inductor esr at 100 khz 1.1 ohm
9 6199a?pmgmt?20-sep-05 at73c211 5.3 ldo1 regulator elect rical characteristics table 5-3. ldo1 electrical characteristics (t amb = -20c to 85c, vin = 3.2v to 4.2v unless otherwise specified) symbol parameter conditions min typ max unit v out output voltage bb1 = 0 2.7 v bb1 = 1 2.8 v i out output current 80 130 ma i qc quiescent current 195 a ? v out line regulation v in : 3v to 3.4v, i out = 130 ma 1 2 mv ? v peak line regulation transient same as above, t r = t f = 5 s 1.5 2.85 mv ? v out load regulation 10% - 90% i out 3mv ? v peak load regulation transient same as above, t r = t f = 5 s 1.2 2.4 mv psrr ripple rejection f = 217 hz; vin = 3.6v 70 73 db v n output noise bw: 10 hz to 100 khz 29 37 v rms t r rise time 100% i out , 10% - 90% v out 50 s i sd shut down current 1a table 5-4. ldo1 external components symbol parameter conditions min typ max unit c out output capacitor value 1.98 2.2 2.42 f c esr output capacitor esr 100 khz 50 mohm
10 6199a?pmgmt?20-sep-05 at73c211 5.4 ldo2 regulator elect rical characteristics table 5-5. ldo2 electrical characteristics (t amb = -20c to 85c, vin = 3.2v to 4.2v unless otherwise specified) symbol parameter conditions min typ max unit v out output voltage 2.8 v i out output current pwm mode (eco-mode = 0) 80 ma ldo mode (eco-mode = 1) 5 ma i qc quiescent current pwm mode (eco-mode = 0) 100 a ldo mode (eco-mode = 1) 10 a ? v out line regulation v in : 3v to 3.4v, i out = 80 ma 1 2 mv ? v peak line regulation transient same as above, t r = t f = 5 s 1.5 2.85 mv ? v out load regulation 10% - 90% i out, vin = 3v 3 mv ? v peak load regulation transient same as above, t r = t f = 5 s 1.2 2.4 mv psrr ripple rejection f = 217 hz; vin = 3.6v 70 73 db v n output noise bw: 10 hz to 100 khz 29 37 v rms t r rise time 100% i out , 10% - 90% v out 50 s i sd shut down current 1a table 5-6. ldo2 external components symbol parameter conditions min typ max unit c out output capacitor value 1.98 2.2 2.42 f c esr output capacitor esr 100 khz 50 mohm
11 6199a?pmgmt?20-sep-05 at73c211 5.5 ldo3 regulator elect rical characteristics table 5-7. ldo3 electrical characteristics (t amb = -20c to 85c, vin = 3.2v to 4.2v unless otherwise specified) symbol parameter conditions min typ max unit v out output voltage 2.8 v i out output current 80 130 ma i qc quiescent current 195 a ? v out line regulation v in : 3v to 3.4v, i out = 130 ma 1 2 mv ? v peak line regulation transient same as above, t r = t f = 5 s 1.5 2.85 mv ? v out load regulation 10% - 90% i out, vin = 3v 3 mv ? v peak load regulation transient same as above, t r = t f = 5 s 1.2 2.4 mv psrr ripple rejection f = 217 hz; vin = 3.6v 70 73 db v n output noise bw: 10 hz to 100 khz 29 37 v rms t r rise time 100% i out , 10% - 90% v out 50 s i sd shut down current 1a table 5-8. ldo3 external components symbol parameter conditions min typ max unit c out output capacitor value 1.98 2.2 2.42 f c esr output capacitor esr 100 khz 50 mohm
12 6199a?pmgmt?20-sep-05 at73c211 5.6 ldo4 regulator elect rical characteristics table 5-9. ldo4 electrical characteristics (t amb = -20c to 85c, vin = 3.2v to 4.2v unless otherwise specified) symbol parameter conditions min typ max unit v out output voltage bb1 = 0 2.47 v bb1 = 1 2.66 v i out output current 2ma i qc quiescent current 10 a ? v out line regulation v in : 3v to 3.4v, i out = 2 ma 15 mv ? v peak line regulation transient same as above, t r = t f = 5 s 30 mv ? v out load regulation 10% - 90% i out, vin = 3v 15 mv ? v peak load regulation transient same as above, t r = t f = 5 s 20 mv psrr ripple rejection f = 217 hz; vin = 3.6v 50 db i sd shut down current 1a table 5-10. ldo4 external components symbol parameter conditions min typ max unit c out output capacitor value 1.98 2.2 2.42 f c esr output capacitor esr 100 khz 100 mohm
13 6199a?pmgmt?20-sep-05 at73c211 5.7 ldo5 regulator elect rical characteristics table 5-11. ldo5 electrical characteristics (t amb = -20c to 85c, vin = 3.2v to 4.2v unless otherwise specified) symbol parameter conditions min typ max unit v out output voltage bb1 = 0 1.72 v bb1 = 1 2.66 v i out output current 0.5 ma i qc quiescent current 5a ? v out line regulation v in : 3v to 3.4v, i out = 0.5 ma 15 mv ? v peak line regulation transient same as above, t r = t f = 5 s 30 mv ? v out load regulation 10% - 90% i out, vin = 3v 15 mv ? v peak load regulation transient same as above, t r = t f = 5 s 20 mv psrr ripple rejection f = 217 hz; vin = 3.6v 50 db i sd shut down current 1a table 5-12. ldo4 external components symbol parameter conditions min typ max unit c out output capacitor value 65 100 135 nf c esr output capacitor esr 100 khz 20 100 mohm
14 6199a?pmgmt?20-sep-05 at73c211 5.8 package outline (top view) figure 5-1. forty-nine ball fbga package (top view) 7 6 5 4 3 2 1 nc agnd2 vin-rf gnd vin-reg2 bat-rtc agnd b a 7 6 5 4 3 2 1 nc nc avcc v-pad vcc-rtc nc 7 6 5 4 3 2 1 7 6 5 4 3 2 1 7 6 5 4 3 2 1 7 6 5 4 3 2 1 7 6 5 4 3 2 1 gnd nc nc v-core vin-reg1 gnd1 g nc nc gnd nc nc reset-b lx f nc vbatt nc gnd test en-vib vvib e gnd nc nc bb1 on/off nc vin-vib d nc nc nc nc nc cref c en-analog-b eco-mode up-on/off
15 6199a?pmgmt?20-sep-05 at73c211 6. revision history table 6-1. revision history doc. rev. comments change request ref. 6199a first issue.
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